Numerous electronic technologies such as digital computers, video equipment, and telephone systems have facilitated increased productivity and reduced costs in processing information in most areas of business, science, and entertainment. Testing the components is typically an important activity in ensuring proper performance and accurate results. The testing of semiconductor devices often involves performing test operations in accordance with controls referred to as test patterns. Execution of the test patterns typically involves loading and unloading scan chains with test vectors. However, there are a number of factors that can impact testing and traditional testing approaches are often costly and inefficient.
A system on chip (SoC) design is typically composed of several blocks of circuitry, some of which may have similar designs that are used or replicated in different parts of the chips. The several blocks of circuitry are often configured or organized in test blocks or test partitions for purposes of testing the circuitry. Traditional approaches to generating a full set of conventional test patterns targeted at multiple test partitions and executing the test patterns at substantially similar or parallel times is computationally intensive and time consuming. These conventional attempts are often unable to meet limited cost budgets and constrained project schedules.
Design for test (DFT) methodologies have attempted to adapt to the new ecosystem by directing testing techniques to the SoC environment. One goal of many DFT methodologies is to be able to reuse circuit block designs and test patterns from chip to chip. However, traditional scan-test interfaces are usually tightly associated with the design and in a number of cases a derivative chip may have fewer pins available (e.g., based on the target markets, etc.) and non-standard interfaces. The non-standardized scan interfaces and varying pin configurations within and across traditional SoCs can be major impediments to reuse of circuit block designs and test patterns. The interface and pin count differences between chips traditionally means an extensive update and design change is required (causing additional costs and schedule delays in the design cycle). The limited available pads per circuit block for testing can prevent or reduce use of low cost multi-site testing and 3D stacked integrated circuits.